/*
 * linux/arch/sh/kernel/irq_intc2-sh7760.c
 *
 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
 *
 * May be copied or modified under the terms of the GNU General Public
 * License.  See linux/COPYING for more information.                            
 *
 * Interrupt handling for INTC2-based IRQ.
 *
 * These are the "new Hitachi style" interrupts, as present on the 
 * Hitachi 7751 and the STM ST40 STB1.
 *
 * Improvement for SH7760: Takeo Takahashi <takahashi.takeo@renesas.com>
 *
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>

#include <asm/system.h>
#include <asm/io.h>
#include <asm/machvec.h>


#if defined(CONFIG_CPU_SUBTYPE_SH7760)
#define INTC_PRI_GROUP		8
#define INTC_MSK_GROUP		32
#define INTC_MSKCLR_GROUP	32
#define INTC_INTPRI_REGSZ	4
#define INTC_INTMSK_REGSZ	4
#define INTC_INTMSKCLR_REGSZ	4
#endif

struct intc2_data {
	unsigned int addr;	/* Address of Interrupt Priority Register */
	int mask; /*Mask to apply */
};


static struct intc2_data intc2_data[NR_INTC2_IRQS];

static void enable_intc2_irq(unsigned int irq);
static void disable_intc2_irq(unsigned int irq);

/* shutdown is same as "disable" */
#define shutdown_intc2_irq disable_intc2_irq

static void mask_and_ack_intc2(unsigned int);
static void end_intc2_irq(unsigned int irq);

static unsigned int startup_intc2_irq(unsigned int irq)
{ 
	enable_intc2_irq(irq);
	return 0; /* never anything pending */
}

static struct hw_interrupt_type intc2_irq_type = {
	"INTC2-IRQ",
	startup_intc2_irq,
	shutdown_intc2_irq,
	enable_intc2_irq,
	disable_intc2_irq,
	mask_and_ack_intc2,
	end_intc2_irq
};

static void disable_intc2_irq(unsigned int irq)
{
	unsigned addr;
	int offset=irq-INTC2_FIRST_IRQ;
	unsigned val,flags;

	// Sanity check
	if(offset<0 || offset>=NR_INTC2_IRQS) return;

#if defined(CONFIG_CPU_SUBTYPE_SH7760)
	addr=intc2_data[offset].addr+INTC2_INTMSK_OFFSET +
		((offset/INTC_MSK_GROUP) * INTC_INTMSK_REGSZ);
#if 0
printk(__func__ ": INTMSK(0x%08x)=0x%08x\n", intc2_data[offset].addr+
		INTC2_INTMSK_OFFSET+
		((offset/INTC_MSK_GROUP)*INTC_INTMSK_REGSZ),
		intc2_data[offset].mask);
#endif
#else
	addr=intc2_data[offset].addr+INTC2_INTMSK_OFFSET;
#endif

#if defined(CONFIG_RTHAL)
		hard_save_flags_and_cli(flags);
#else
		save_and_cli(flags);
#endif
	val=ctrl_inl(addr);
	val|=intc2_data[offset].mask;
	ctrl_outl(val,addr);

#if defined(CONFIG_RTHAL)
		hard_restore_flags(flags);
#else
		restore_flags(flags);
#endif
}

static void enable_intc2_irq(unsigned int irq)
{
	int offset=irq-INTC2_FIRST_IRQ;

	// Sanity check
	if(offset<0 || offset>=NR_INTC2_IRQS) return;

#if defined(CONFIG_CPU_SUBTYPE_SH7760)
	ctrl_outl(intc2_data[offset].mask,
		  intc2_data[offset].addr+INTC2_INTMSKCLR_OFFSET+
			((offset/INTC_MSKCLR_GROUP)*INTC_INTMSKCLR_REGSZ));
#if 0
printk(__func__ ": INTMSKCLR(0x%08x)=0x%08x\n", intc2_data[offset].addr+
		INTC2_INTMSKCLR_OFFSET+
		((offset/INTC_MSKCLR_GROUP)*INTC_INTMSKCLR_REGSZ),
		intc2_data[offset].mask);
#endif
#else
	ctrl_outl(intc2_data[offset].mask,
		  intc2_data[offset].addr+INTC2_INTMSKCLR_OFFSET);
#endif

}

static void mask_and_ack_intc2(unsigned int irq)
{
	disable_intc2_irq(irq);
}

static void end_intc2_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_intc2_irq(irq);
}

void make_intc2_irq(unsigned int irq, unsigned int addr, 
		    unsigned int group,int pos, int priority)
{
	int offset=irq-INTC2_FIRST_IRQ;
	unsigned flags,val;

	if(offset<0 || offset>=NR_INTC2_IRQS) {
		return;
	}

	disable_irq_nosync(irq);
	/* Fill the the data we need */

#if defined(CONFIG_CPU_SUBTYPE_SH7760)
	/*
	 * addr is the top address of priority register.
	 * That is INTPRI00 register address.
	 */
	intc2_data[offset].addr=addr;

	/*
 	 * pos is the position of interrupt mask bit in
	 * both INTMSK and INTMSKCLR register.
	 */
	intc2_data[offset].mask=1<<pos;

	/* Set the priority level */
#if defined(CONFIG_RTHAL)
		hard_save_flags_and_cli(flags);
#else
		save_and_cli(flags);
#endif

	/* an INTPRI contains 8 group */
	val=ctrl_inl(addr+INTC2_INTPRI_OFFSET+
			((offset/INTC_PRI_GROUP) * INTC_INTPRI_REGSZ));
	/* 
	 *       31-28 27-24 23-20 19-16 15-12 11-8  7-4   3-0
	 *      +-----+-----+-----+-----+-----+-----+-----+-----+
	 * gourp|  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  | 
	 *      +-----+-----+-----+-----+-----+-----+-----+-----+
	 */
	val|=(priority)<< (group * 4);
	ctrl_outl(val,addr+INTC2_INTPRI_OFFSET+
				((offset/INTC_PRI_GROUP) * INTC_INTPRI_REGSZ));
/*
printk(__func__ ": INTPRI(0x%08x)=0x%08x\n", addr+INTC2_INTPRI_OFFSET+
		((offset/INTC_PRI_GROUP)*INTC_INTPRI_REGSZ), val);
*/
#else
	intc2_data[offset].addr=addr;
	intc2_data[offset].mask=1<<pos;
		
	/* Set the priority level */
#if defined(CONFIG_RTHAL)
		hard_save_flags_and_cli(flags);
#else
		save_and_cli(flags);
#endif
	val=ctrl_inl(addr+INTC2_INTPRI_OFFSET);
	val|=(priority)<< (group<<4);
	ctrl_outl(val,addr+INTC2_INTPRI_OFFSET);
#endif
#if defined(CONFIG_RTHAL)
		hard_restore_flags(flags);
#else
		restore_flags(flags);
#endif

	irq_desc[irq].handler=&intc2_irq_type;

	disable_intc2_irq(irq);
}



