#ifndef BVDD_P_INCLUDED
#define BVDD_P_INCLUDED

#ifdef DEBUG
# define PRINT_DEBUG(x...) printk(KERN_WARNING DEVICE_NAME ": " x)
# define PRINT_INFO(x...) printk(KERN_WARNING DEVICE_NAME ": " x)
# define PRINT_WARN(x...) printk(KERN_WARNING DEVICE_NAME ": " x)
# define PRINT_ERROR(x...) printk(KERN_ERR DEVICE_NAME ": " x)
# define PRINT_FATAL(x...) printk(KERN_CRIT DEVICE_NAME ": " x)
#else
# define PRINT_DEBUG(x...)
# define PRINT_INFO(x...)  printk(KERN_WARNING DEVICE_NAME ": " x)
# define PRINT_WARN(x...) printk(KERN_WARNING DEVICE_NAME ": " x)
# define PRINT_ERROR(x...) printk(KERN_ERR DEVICE_NAME ": " x)
# define PRINT_FATAL(x...) printk(KERN_CRIT DEVICE_NAME ": " x)
#endif

#define DEVICE_NAME "bvdd"	/* The name for our device */

typedef struct {
    unsigned long FDADR;	/* frame descriptor address */
    unsigned long FSADR;      /* DMA Frame Source Address Registers */
    unsigned long FIDR;		/* frame id reg */
    unsigned long LDCMD;	/* LCD command reg */
} descriptor_t;

#ifndef USE_PXAFB_DESCRIPTOR_AREA
# define DESCRIPTORS_SIZE (PAGE_SIZE)
# define MAX_DESCRIPTORS (DESCRIPTORS_SIZE / 16)
#else
# define DESCRIPTORS_SIZE (PAGE_SIZE - 16)
# define MAX_DESCRIPTORS (DESCRIPTORS_SIZE / 16)
#endif

#define LAYER_BASE 0
#define LAYER_OVERLAY1 1
#define LAYER_OVERLAY2 2

#include <asm/hardware.h>
#undef FDADR

#define REG_LCCR0	__REG(0x44000000) /* LCD Controller Control register 0 */
#define REG_LCCR1	__REG(0x44000004) /* LCD Controller Control register 1 */
#define REG_LCCR2	__REG(0x44000008) /* LCD Controller Control register 2 */
#define REG_LCCR3	__REG(0x4400000C) /* LCD Controller Control register 3 */
#define REG_LCCR4	__REG(0x44000010) /* LCD Controller Control register 4 */
#define REG_LCCR5	__REG(0x44000014) /* LCD Controller Control register 5 */
#define REG_FBR0	__REG(0x44000020)
#define REG_FBR1	__REG(0x44000024)
#define REG_FBR2	__REG(0x44000028)
#define REG_FBR3	__REG(0x4400002C)
#define REG_FBR4	__REG(0x44000030)
#define REG_LCSR1	__REG(0x44000034)
#define REG_LCSR0	__REG(0x44000038)
#define REG_LIIDR	__REG(0x4400003C)
#define REG_TRGBR	__REG(0x44000040)
#define REG_TCR		__REG(0x44000044)
#define REG_OVL1C1	__REG(0x44000050)
#define REG_OVL1C2	__REG(0x44000060)
#define REG_OVL2C1	__REG(0x44000070)
#define REG_OVL2C2	__REG(0x44000080)
#define REG_CCR		__REG(0x44000090)
#define REG_CMDCR	__REG(0x44000100)
#define REG_PRSR	__REG(0x44000104)
#define REG_FBR5	__REG(0x44000110)
#define REG_FBR6	__REG(0x44000114)
#define REG_FDADR0	__REG(0x44000200)
#define REG_FSADR0	__REG(0x44000204)
#define REG_FIDR0	__REG(0x44000208)
#define REG_LDCMD0	__REG(0x4400020C)
#define REG_FDADR1	__REG(0x44000210)
#define REG_FSADR1	__REG(0x44000214)
#define REG_FIDR1	__REG(0x44000218)
#define REG_LDCMD1	__REG(0x4400021C)
#define REG_FDADR2	__REG(0x44000220)
#define REG_FSADR2	__REG(0x44000224)
#define REG_FIDR2	__REG(0x44000228)
#define REG_LDCMD2	__REG(0x4400022C)
#define REG_FDADR3	__REG(0x44000230)
#define REG_FSADR3	__REG(0x44000234)
#define REG_FIDR3	__REG(0x44000238)
#define REG_LDCMD3	__REG(0x4400023C)
#define REG_FDADR4	__REG(0x44000240)
#define REG_FSADR4	__REG(0x44000244)
#define REG_FIDR4	__REG(0x44000248)
#define REG_LDCMD4	__REG(0x4400024C)
#define REG_FDADR5	__REG(0x44000250)
#define REG_FSADR5	__REG(0x44000254)
#define REG_FIDR5	__REG(0x44000258)
#define REG_LDCMD5	__REG(0x4400025C)
#define REG_FDADR6	__REG(0x44000260)
#define REG_FSADR6	__REG(0x44000264)
#define REG_FIDR6	__REG(0x44000268)
#define REG_LDCMD6	__REG(0x4400026C)
#define REG_LCDBSCNTR	__REG(0x48000054)

typedef struct {
    unsigned long ENB		: 1; /* LCD Controller Enable */
    unsigned long CMS		: 1; /* Color/Monochrome Select */
    unsigned long SDS		: 1; /* Single-Scan/dual-scan Display Select */
    unsigned long LDM		: 1; /* LCD Disable Done Mask */
    unsigned long SOFM0		: 1; /* Start of Frame Mask for Channel 0 and Channel 1 (Dual Scan) */
    unsigned long IUM		: 1; /* Input FIFO Underrun Mask */
    unsigned long EOFM0		: 1; /* End of Frame Mask for Channel 0 and for Channel 1 (Dual Scan) */
    unsigned long PAS		: 1; /* Passive/Active Display Select */
    unsigned long reserved2	: 1;
    unsigned long DPD		: 1; /* Double-Pixel Data (DPD) Pin Mode */
    unsigned long DIS		: 1; /* LCD Disable */
    unsigned long QDM		: 1; /* LCD Quick Disable Mask */
    unsigned long PDD		: 8; /* Palette DMA Request Delay */
    unsigned long BSM0		: 1; /* Branch Status Mask */
    unsigned long OUM		: 1; /* Output FIFO Underrun Mask */
    unsigned long LCDT		: 1; /* LCD Panel Type */
    unsigned long RDSTM		: 1; /* LCD Read Status Interrupt Mask */
    unsigned long CMDIM		: 1; /* LCD Command Interrupt Mask */
    unsigned long OUC		: 1; /* Overlay Underlay Control Bit */
    unsigned long LDDALT	: 1; /* LDD Alternate Mapping Control Bit */
    unsigned long reserved1     : 5;
} LCCR0_t;
typedef union {
    LCCR0_t f;
    unsigned long val;
} LCCR0_u;

typedef struct {
    unsigned long PPL		:10; /* Pixels per Line for the Base Frame */
    unsigned long HSW		: 6; /* Horizontal Sync Pulse Width */
    unsigned long ELW		: 8; /* End-of-Line Pixel Clock Wait Count */
    unsigned long BLW		: 8; /* Beginning-of-Line Pixel Clock Wait Count */
} LCCR1_t;
typedef union {
    LCCR1_t f;
    unsigned long val;
} LCCR1_u;

typedef struct {
    unsigned long LPP		:10; /* Lines per Panel for the Base Frame */
    unsigned long VSW		: 6; /* Vertical Sync Pulse Width */
    unsigned long EFW		: 8; /* End-of-Frame Line Clock Wait Count */
    unsigned long BFW		: 8; /* Beginning-of-Frame Line Clock Wait Count */
} LCCR2_t;
typedef union {
    LCCR2_t f;
    unsigned long val;
} LCCR2_u;

typedef struct {
    unsigned long PCD		: 8; /* Pixel Clock Divisor */
    unsigned long ACB		: 8; /* AC Bias Pin Frequency */
    unsigned long API		: 4; /* AC Bias Pin Transitions per Interrupt */
    unsigned long VSP		: 1; /* Vertical Sync Polarity */
    unsigned long HSP		: 1; /* Horizontal Sync Polarity */
    unsigned long PCP		: 1; /* Pixel Clock Polarity */
    unsigned long OEP		: 1; /* Output Enable Polarity */
    unsigned long BPP		: 3; /* Bits per Pixel */
    unsigned long DPC		: 1; /* Double Pixel Clock Mode */
    unsigned long reserved1	: 1;
    unsigned long BPP3		: 1; /* Bits per Pixel */
    unsigned long PDFOR		: 2; /* Pixel Data Format */
} LCCR3_t;
typedef union {
    LCCR3_t f;
    unsigned long val;
} LCCR3_u;

typedef struct {
    unsigned long K1		: 3; /* Multiplication Constant for Red for Half Transparency */
    unsigned long K2		: 3; /* Multiplication Constant for Blue for Half Transparency */
    unsigned long K3		: 3; /* Multiplication Constant for Green for Half Transparency */
    unsigned long reserved2	: 6;
    unsigned long PAL_FOR	: 2; /* Palette Data Format */
    unsigned long reserved1	:12;
    unsigned long PCDDIV	: 1; /* PCD Divisor Selection */
} LCCR4_t;
typedef union {
    LCCR4_t f;
    unsigned long val;
} LCCR4_u;

/* LCCR5 unused */

typedef struct {
    unsigned long PPL1		:10; /* Pixels per Line for Overlay 1 Frame */
    unsigned long LPO1		:10; /* Number of Lines for Overlay 1 */
    unsigned long BPP1		: 4; /* Bits per Pixel for Overlay 1 */
    unsigned long reserved1	: 7;
    unsigned long O1EN		: 1; /* Enable bit for Overlay 1 */
} OVL1C1_t;
typedef union {
    OVL1C1_t f;
    unsigned long val;
} OVL1C1_u;

typedef struct {
    unsigned long O1XPOS	:10; /* Horizontal Position of the Upper Left-Most Pixel of Overlay 1 Window */
    unsigned long O1YPOS	:10; /* Vertical Position of the Upper Left-Most Pixel of Overlay 1 Window */
    unsigned long reserved1	:12;
} OVL1C2_t;
typedef union {
    OVL1C2_t f;
    unsigned long val;
} OVL1C2_u;

typedef struct {
    unsigned long PPL2		:10; /* Pixels per Line for Overlay 2 Frame */
    unsigned long LPO2		:10; /* Number of Lines for Overlay 2 Frame */
    unsigned long BPP2		: 4; /* Bits per Pixel for Overlay 2 */
    unsigned long reserved1	: 7;
    unsigned long O2EN		: 1; /* Overlay 2 Enable */
} OVL2C1_t;
typedef union {
    OVL2C1_t f;
    unsigned long val;
} OVL2C1_u;

typedef struct {
    unsigned long O2XPOS	:10; /* Horizontal Position of the Upper Left Most Pixel of Overlay 2 */
    unsigned long O2YPOS	:10; /* Vertical Position of the Upper Left Most Pixel of Overlay 2 */
    unsigned long FOR		: 3; /* Format */
    unsigned long reserved1	: 9;
} OVL2C2_t;
typedef union {
    OVL2C2_t f;
    unsigned long val;
} OVL2C2_u;

#undef BS0
typedef struct {
    unsigned long LDD		: 1; /* LCD Disable Done Flag */
    unsigned long SOF0		: 1; /* Start of Frame Status for Base */
    unsigned long BER		: 1; /* Bus Error Status */
    unsigned long ABC		: 1; /* AC Bias Count Status */
    unsigned long IU0		: 1; /* Input FIFO Underrun for Channel 0 */
    unsigned long IU1		: 1; /* Input FIFO Underrun for Channel 1 */
    unsigned long OU		: 1; /* Output FIFO Underrun */
    unsigned long QD		: 1; /* LCD Quick Disable Status */
    unsigned long EOF0		: 1; /* End of Frame Status for Base (Channel 0) */
    unsigned long BS0		: 1; /* Branch Status for Base */
    unsigned long SINT		: 1; /* Subsequent Interrupt Status */
    unsigned long RD_ST		: 1; /* Read Status */
    unsigned long CMD_INT	: 1; /* Command Interrupt Status */
    unsigned long reserved2	:15;
    unsigned long BER_CH	: 3; /* Bus Error Channel Number */
    unsigned long reserved1	: 1;
} LCSR0_t;
typedef union {
    LCSR0_t f;
    unsigned long val;
} LCSR0_u;

#undef BS1
typedef struct {
    unsigned long SOF1		: 1; /* Start of Frame Status for Channel 1 */
    unsigned long SOF2		: 1; /* Start of Frame Status for Channel 2 */
    unsigned long SOF3		: 1; /* Start of Frame Status for Channel 3 */
    unsigned long SOF4		: 1; /* Start of Frame Status for Channel 4 */
    unsigned long SOF5		: 1; /* Start of Frame Status for Channel 5 */
    unsigned long SOF6		: 1; /* Start of Frame Status for Channel 6 */
    unsigned long reserved4	: 2;
    unsigned long EOF1		: 1; /* End of Frame Status for Channel 1 */
    unsigned long EOF2		: 1; /* End of Frame Status for Channel 2 */
    unsigned long EOF3		: 1; /* End of Frame Status for Channel 3 */
    unsigned long EOF4		: 1; /* End of Frame Status for Channel 4 */
    unsigned long EOF5		: 1; /* End of Frame Status for Channel 5 */
    unsigned long EOF6		: 1; /* End of Frame Status for Channel 6 */
    unsigned long reserved3	: 2;
    unsigned long BS1		: 1; /* Branch Status for Channel 1 (Command Register) */
    unsigned long BS2		: 1; /* Branch Status for Channel 2 (Command Register) */
    unsigned long BS3		: 1; /* Branch Status for Channel 3 (Command Register) */
    unsigned long BS4		: 1; /* Branch Status for Channel 4 (Command Register) */
    unsigned long BS5		: 1; /* Branch Status for Channel 5 (Command Register) */
    unsigned long BS6		: 1; /* Branch Status for Channel 6 (Command Register) */
    unsigned long reserved2	: 3;
    unsigned long IU2		: 1; /* Input FIFO Underrun for Channel 2 */
    unsigned long IU3		: 1; /* Input FIFO Underrun for Channel 3 */
    unsigned long IU4		: 1; /* Input FIFO Underrun for Channel 4 */
    unsigned long IU5		: 1; /* Input FIFO Underrun for Channel 5 */
    unsigned long IU6		: 1; /* Input FIFO Underrun for Channel 6 */
    unsigned long reserved1	: 2;
} LCSR1_t;
typedef union {
    LCSR1_t f;
    unsigned long val;
} LCSR1_u;

/* CCR unused */
/* CMDCR unused */
/* TRGBR unused */
/* TCR unused */

typedef struct {
    unsigned long LCDBS		: 4; /* LCD Buffer Strength */
    unsigned long reserved1	:28;
} LCDBSCNTR_t;
typedef union {
    LCDBSCNTR_t f;
    unsigned long val;
} LCDBSCNTR_u;

typedef struct {
    LCCR0_u lccr0;
    LCCR1_u lccr1;
    LCCR2_u lccr2;
    LCCR3_u lccr3;
    LCCR4_u lccr4;
    OVL1C1_u ovl1c1;
    OVL1C2_u ovl1c2;
    OVL2C1_u ovl2c1;
    OVL2C2_u ovl2c2;
    unsigned long fdadr0;
    unsigned long fdadr1;
    unsigned long fdadr2;
    unsigned long fdadr3;
    unsigned long fdadr4;
    unsigned long fdadr5;
    unsigned long fdadr6;
    char cken20_intmem;
} lcdc_state_t;

#endif /* BVDD_P_INCLUDED */
